Company Overview

The Challenge

The rapid increase in integrated circuit size and complexity, coupled with the smaller feature sizes, has caused significant challenges to the design community in adopting nanometer process technology. Nanometer geometries introduce challenges in timing delay, power consumption, signal integrity, power supply variation and electro-migration.

Due to the inadequacies of traditional verification technologies, designers are forced to divide their transistors into smaller blocks for verification, thereby sacrificing the accuracy of their simulation and analysis. Inaccurate simulation of interdependent nanometer effects are the cause of catastrophic chip failures, functional failures, or degraded system performance. Iterative chip fabrication runs are the result, often costing one half million dollars or more per iteration. This also lengthens schedule, burns additional engineering hours, delays time-to-market, and decreases the market potential of the eventual products based upon the chip.

Power Consumption

Power consumption continues to grow in importance. Supply voltages are continually trending lower as geometries continue scaling downward. Reduced voltages cause active devices to operate closer to their switching thresholds and, as a result, never fully turn off. Smaller transistors also have reduced channel lengths, causing a decrease in threshold voltages. This causes increased leakage currents (source to drain currents that are known as subthreshold leakage currents). Additional leakage also takes place from the gate to drain as well as source and drain to substrate. In cumulative, leakage power, due to higher leakage currents, contributes up to 50% of the chip's total power consumption. Effectively managing the power consumption requires more accurate simulation and management of all sources of power (switching, leakage and hidden.)

Supply Variation

Supply voltage variations, commonly known as IR drop, is a function of the current (I) drawn from the power grid and the resistance (R) of the interconnect. If the current demand is higher than anticipated, or the wire resistance is too large, supply voltage drops below what is required. This causes larger gate and signal delays, timing discrepancies in signals and clock skew. IR drop on power and ground grids can also affect the noise margins and compromise the signal integrity of the design.

Noise

With nanometer scaling, the height of the interconnect becomes greater than the width, and the coupling between adjacent parallel interconnect lines is now greater than the coupling of interconnect between lines. As signals (currents) travel along the interconnect, glitches or crosstalk with neighboring nets ("victim" nets) can occur, given the relative rate of switching (rise and fall times of the signals) and the amount of mutual capacitance. If the amplitude and timing of the glitch occurs at a critical moment, it may cause a cell to accelerate or slow its transitioning, or even exceed the logic threshold of the receiver cell and force a transition that should not take place. To avoid these types of timing problems or functional failures, accurate simulation of these noise effects is essential.

The Need

The interesting characteristic that binds all of these nanometer effects together is that they are current-based problems. They are also transient and interdependent. The ideal approach to analyze and prevent these problems from adversely impacting designs, prior to fabrication, would be current-based, and would take into account the transient and interdependent nature of nanometer effects.

The Solution

Nascentric has developed unique current-based technologies to address nanometer effects, and owns a diverse, valuable patent portfolio in this and many other unique verification and analysis techniques. Nascentric is the first and only company to develop SPICE entirely based on current instead of voltage, which has significant advantages in performance, accuracy and capacity over traditional SPICE, particularly as integrated circuit geometries shrink and leakage currents grow.

A privately held company, Nascentric Inc. was founded in October 2003. Headquartered in Austin, Texas, the company is led by an experienced EDA management team, an industry recognized Board of Directors, and has assembled a highly respected technical advisory board. Nascentric's principle investors include Intel Capital, Austin Ventures, Needham Partners, and Silverton Partners.